1. Field of the Invention
The present invention relates to methods of manufacturing semiconductor devices, and more particularly to a method of manufacturing a semiconductor device having a DRAM capacitor.
2. Description of the Background Art
A conventional method of manufacturing a semiconductor device having a DRAM capacitor has the following steps, which are carried out in the following order: (a) partially forming an element isolating insulation film in an upper surface of a silicon substrate, (b) ion-implanting an impurity in a direction perpendicular to the upper surface of the silicon substrate to form a doped channel region, a channel cut region, and a well region, all of which are of p-type, within the silicon substrate that is in an element forming region, (c) forming a gate insulating film on the upper surface of the silicon substrate that is within the element forming region using a thermal oxidation technique, (d) forming a gate electrode on the gate insulating film, (e) forming a source region and a drain region, both of which are of n-type, in the upper surface of the silicon substrate, the source region and drain region forming a pair such as to sandwich a channel forming region below the gate electrode, (f) forming a first interlayer dielectric film entirely, (g) forming a first contact plug connected to the drain region in the first interlayer dielectric film, (h) forming a bit line connected to the first contact plug, (i) forming a second interlayer dielectric film entirely, (j) forming a second contact plug connected to the source region in the first and second interlayer dielectric films, (k) forming a third interlayer dielectric film entirely, (j) forming a capacitor lower electrode connected to the second contact plug in the third interlayer dielectric film, (m) forming a capacitor dielectric film on the capacitor lower electrode, and (n) forming a capacitor upper electrode on the capacitor dielectric film.
Japanese Patent Application Laid-Open Nos. 10-65153, 9-237829, and 8-250583, for example, disclose methods of manufacturing a semiconductor device including the step of forming a doped channel region in a silicon substrate.
According to the conventional methods of manufacturing a semiconductor device, however, the gate insulating film is formed after the doped channel region is formed. For this reason, part of the impurity contained in the doped channel region is absorbed into the gate insulating film by the heat treatment for forming the gate insulating film. As a result, the impurity concentration of the doped channel region becomes lower than a desired value, thereby reducing the threshold voltage of a memory cell transistor. This tendency is particularly noticeable in a boundary portion between the element isolating insulation film and the doped channel region, and a considerable reduction in the threshold voltage of memory cell transistors occurs when the width of the doped channel region becomes narrower than a certain value (the phenomenon known as “inverse narrow width effect”).
It is possible to compensate the reduction in the impurity concentration by ion-implanting a p-type impurity at a higher concentration than a desired value when forming doped channel regions. However, since the high-concentration p-type impurity is implanted into the regions in which n-type source and drain regions are to be formed, the following problems arise.
Because the impurity concentration in the source and drain regions reduces, the contact resistance between the source region and the second contact plug increases. As a consequence, the performance of memory cell transistors degrades, leading to the problem of deteriorating data write characteristics.
In addition, electric field strength becomes high in the boundary portion between the source region and the channel forming region and in the boundary portion between the source region and the element isolating insulation film. As a result, junction leakage current increases, leading to the problem of deteriorating device characteristics (for example, refresh characteristics) of DRAMs.